Eran briman of ceva describes reuse of a single dsp architecture for various applications. Utilizing new generation dual cevabx cores with optimizing llvm c compiler for protocol, control, and dsp native c code supports very low overhead rtos multitasking with dynamic branch prediction. Cevateaklite4 is a multifunctional dsp architecture for highperformance. Ceva also provides a library of intrinsic functions compiler. Note that the columns in above table are eitheror, not. Achieving 30% performance gain and 30% code reduction relative to previous generation core. Jan 04, 2019 ceva announced its new allpurpose, hybrid dsp controller architecture to address new algorithms of digital signal processing in voice, video, communication, sensing and digital signal control applications. Figure 1 shows a block diagram of the cevax1620 dsp, a 16bit dual mac implementation derived from the cevax architecture. Ceva bx2 uses quad 32x32bit macs and octal 16x16bit macs, with enhanced capability for supporting 16.
The cevaxc dsp is the perfect choice for our softwaredefined radio chip technology platform, allowing us to develop solutions for a wide range of use cases, ranging from cellular v2x and drone communications, to 5g terminals and satellites. Jul 23, 2007 in contrast, the cevax1641 compiler yields totally different results when tuned for cycle count minimization. The core supports multiple voltage domains associated with the main functional units, such as the dsp logic, the instruction and data memories, and so forth. Ceva x1643 highperformance, low power dsp core compatible with ti c6x code. Tensilica fills out portfolio with dualmac dsp core berkeley. Ceva announces cevabx, a new allpurpose hybrid dsp. Cevax1643 has four multiplyaccumulate mac units and upgrades its predecessor, cevax1641, by adding a data cache, powermanagement unit, and support for wider external buses. The ceva xc323 includes an integrated power scaling unit psu, which provides advanced power management for both dynamic and leakage power. Cevax4 and is a quadcore 128bit wide vliw and simd processor with a 10stage pipeline. A digital signal processor dsp is a specialized microprocessor chip, with its architecture. Snps, a global leader providing software, ip and services used to accelerate innovation in chips and electronic systems today announced that ceva, inc. In contrast, the cevax1641 compiler yields totally different results when tuned for cycle count minimization. The cevax dsp family offers a combination of vliw and simd architectures. The cevabx2 is using an 11stage pipeline and 5way vliw microarchitecture, it offers parallel processing with dual scalar compute engines, loadstore and program control that reaches a speed of 2 ghz at a tsmc 7nm process node using common standard cells and memory compilers.
Offering general purpose dsp capabilities required for motor control and electrification, the ceva bx architecture extends ceva s market reach into the burgeoning automotive and industrial markets currently underserved by legacy dsps or mpumcus with low performance dsp coprocessing. Ceva coaxes designers to move to its cevax and cevaxc dsp ip. Cevaxc323tm the cevaxc323 is a highly powerful nextgeneration communication dsp core that fully addresses todays requirements for extreme processing, flexibility, scalability, and ultralow power consumption. Ceva bx offers a new breed of dsp architecture, combining. Quite a starting package for application developers. Build your own edge ai soc with sifive riscv cpus and ceva. This framework is comprehensive enough in order to support various processing demands, from a 2 mac dsp design up to 8 mac dsp.
The cevaxm6 vision processor core boosts performance for. A digital signal processor dsp is a specialized microprocessor or a sip block chip, with its architecture optimized for the operational needs of digital signal processing. Ceva unveils worlds most powerful dsp architecture gen4 ceva xc architecture offers highest performance of 1,600 gops, innovative dynamic multithreading and advanced pipeline to reach operating. Ceva dsp multiplies execution units for mimo 5g tech design. Compiler optimization for dsp applications ee times. Dsps are fabricated on mos integrated circuit chips. Even with modern compiler optimizations handoptimized assembly code is. Understanding the reuse of a dsp architecture for different designs. The cevabx architecture revolutionizes the allpurpose dsp concept by offering a high performance hybrid architecture that is a single compute island for all dsp and control workloads that are commonplace in intelligent connected devices. The company develops semiconductor intellectual property core technologies for multimedia and wireless communications technology. The cevaxc323 dsp architecture is compiler driven, implementing an orthogonal instruction set so as to. The ceva xc16 dsp is evidence of this and serves to substantially reduce the entry barriers for oems and semiconductor vendors looking to benefit from the growing 5g capex and open ran network architectures.
Latest cevabx hybrid dsp controller features a coremarkmhz. Having all that logic in one device would be an advantage, and that is whats offered by the cevabx hybrid dspcontroller. The core can either process 16 bit or 32bit native data word sizes. Ceva, the largest independent supplier of dsp intellectual property ip, has introduced two new dsp cores. The ceva xc16 is available for general licensing starting in q2 2020.
Cevabx comes with extensive software libraries, both fundamental dsp neural net, neural net frameworks, compiler, debugger and rtos and application cellular iot and gnss isa extensions, ceva clearvox noise reduction for voiceactivated systems and ceva voice recognition. Jan 04, 2019 the dsp part is to handle things like noise reduction and speech recognition, while digital signal control is used for phy and motor control, as well as sensorfusion. Cevax4 is intended for the highest tier of smart phones which will be able to download 1gbits data during a voice conversation. Here is a simple multiplyandaccumulate mac loop to demonstrate loop unrolling and swp. The ceva bx2 is using an 11stage pipeline and 5way vliw microarchitecture, it offers parallel processing with dual scalar compute engines, loadstore and program control that reaches a speed of 2 ghz at a. The cevabx2 addresses intensive workloads such as 5g phy control, multimicrophone. Synopsys and ceva deliver superior performance, power and. More than 8 billion ceva powered products have shipped to date.
Jan 07, 2019 ceva announced a new hybrid dsp controller architecture. Using an 11stage pipeline and 5way vliw microarchitecture, it offers parallel processing with dual scalar compute engines, loadstore and program control that reaches a speed of 2 ghz at tsmc 7nm process node. Cevateakliteiii digital signal processing core berkeley design. Emmanuel gresset, business development director at ceva, said the xc12 core provides a major increase in terms of horsepower. Ceva investor relations headquartered in mountain view, california, ceva is the leading licensor of cellular, multimedia and connectivity technologies to semiconductor companies and oems serving the mobile, consumer, automotive and iot markets. Cevax debugger 5 19892019 lauterbach gmbh warning warning. The ceva deep neural network cdnn is a comprehensive compiler technology that creates fullyoptimized runtime software for senspro sensor hub dsps, neupro ai processors and cevaxm vision dsps. In the example below we can see the cevax1641 compiler in full power, utilizing every bit of hardware the cevax1641 quad mac architecture has to offer. The cevateakliteiii is a 32bit licensable dsp processor core from ceva that builds on the. Ceva was created through the combination of the dsp ip licensing division of dsp. Autotalks license and deploy ceva dsp for massmarket v2x chipset.
Cevabx is a new breed of dsp architecture, combining the inherent low power requirements of dsp kernels with highlevel programming and compact code size requirements of a large control code base. In the example below we can see the cevax1641 compiler in full power, utilizing every bit of hardware the cevax1641 quadmac. Ceva is the leading provider of ultralowpower ip for vision, deep learning, audio, communication and connectivity. The cevaxc16 dsp is based on a unified scalar and vectorprocessing platform, using two independent scalar cores, sharing the same coherent tightly coupled memory subsystem, to facilitate true simultaneous and symmetric multithreading operation. Cevabx2 uses quad 32x32bit macs and octal 16x16bit macs, with enhanced capability for supporting 16x8bit and 8x8bit mac operations. Cevas latest iteration of its xc architecture aims at the intensive dsp required for 5g basestations. Ceva bx2 is a multipurpose hybrid dsp and controller, designed for the inherent low power requirements of dsp kernels with highlevel programming and compact code size requirements of a large control code base. Ceva teakliteiii targets a range of portable and highdefinition audio applications, along with voip and cellular baseband. Wide angle imaging immervision patented image processing algorithms facilitate dramatic improvements in image quality and remove inherent distortions associated with the use of wideangle cameras. Jan 07, 2019 moshe sheier, vice president of marketing at ceva, commented.
Integrated mac resources in the last three generations of ceva vision processing cores. The highlighted adds instruction follows the cevax1641 compilers calling. Ceva bx1 is a multipurpose hybrid dsp and controller designed for the inherent low power requirements of dsp kernels with highlevel programming and compact code size requirements of a large control code base. Ceva was created in november 2002, through the combination of the dsp ip licensing division of dsp group and parthus technologies plc an irish company that was founded in 1993.
An independent analysis of the cevateakliteiii digital. Aug 04, 2011 ceva is the worlds leading licensor of silicon intellectual property sip dsp cores and platform solutions for the mobile handset, portable and consumer electronics markets. The level of parallelism supported is also variable, as well as the memory subsystem structure and the system if. For 16 mac with 512bit bandwidth, only 176 bits actually loaded. The cevabx family is accompanied by a comprehensive software development tool chain, including an advanced llvm compiler, eclipse based debugger, dsp and neural network compute libraries, neural network frameworks support such as android nn api, arm nn, and tensorflow lite, and choice of real time operating systems rtos. The pioneering cevax dsp architecture is based on the concept of such an architecture framework. Features include quad 32x32bit macs and octal 16x16bit macs, with enhanced support for 16. The ceva teakliteiii is a 32bit licensable dsp processor core from ceva that builds on the legacy of the ceva teaklite, ceva teakliteii, and ceva teak cores. Ceva states that the x1620 core is no longer offered for license and has. High level programmable modern general purpose dsp architecture for a broad. Understanding the reuse of a dsp architecture for different. The ceva deep neural network cdnn is a comprehensive compiler technology that creates fullyoptimized runtime software for senspro sensor hub dsps, neupro ai processors and.
New cevax delivers 2x more dsp horsepower while consuming 50% less power than the previous generation cevax, said the firm. The cevaxc323 dsp architecture is compilerdriven, implementing an orthogonal instruction set so as to. The dsp core features 128 mac units that can run in parallel with the neupro engine. To prevent debugger and target from damage it is recommended to connect or disconnect the debug cable only while the target power is off. Ceva, the leading licensor of wireless connectivity and smart sensing technologies, today announced the unveiling of the worlds most powerful dsp architecture, the gen4 ceva xc. As dsp processors become more powerful and compiler optimization. New and improved isa for accelerating fft and symmetric fir.
Ceva announced a new hybrid dspcontroller architecture. Todays audio, voice, and speech processing applications challenge designers to manage a wide. Below is a rather inefficient yet compact assembly code excerpt generated when the cevax1641 dsp core compiler was tuned for code size minimization. Oct 10, 2016 hard on the heels of the public release of ceva s secondgeneration convolutional neural network toolset, cdnn2, the company is putting the final touches on its fifthgeneration processor core, the ceva xm6, designed to run software generated by that toolset. Mar 07, 20 ceva is the worlds leading licensor of silicon intellectual property dsp cores and platform solutions for the mobile, portable and consumer electronics markets. The cdnninvite api offers software engineers a unified programming model, and it enables cevas customers to differentiate their designs by building diverse applicationspecific accelerators. Ceva, a leading licensor of silicon intellectual property sip dsp cores and platform solutions, has utilized synopsys design compiler graphical rtl. Disconnect the debug cable from the target while the target power is off. The cevabx is initially offered in two configurations the cevabx1 with single 32x32bit mac and quad 16x16bit macs and the cevabx2 with quad 32x32bit macs and octal 16x16bit macs, that are also capable of supporting 16x8bit and 8x8bit mac operations. All four mac units are used simultaneously and the entire 128bit memory. Ceva utilizes synopsys design compiler graphical to achieve. Targeted for massmarket embedded devices, cdnn incorporates a broad range of network optimizations, advanced quantization algorithms, data flow management and fullyoptimized compute cnn and rnn libraries into a holistic solution that enables cloudtrained ai models to be deployed on edge devices. A tms320 digital signal processor chip found in a guitar effects unit.
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